Multifunctional integrated circuits (ICs) often combine analog and digital circuits and signals, requiring the IC to support multiple sampling rates. In the example of a wireless transceiver circuit, a digital signal chain receives a signal through the analog front-end circuit, which is converted to a digital signal by an analog-to-digital converter (ADC) at a first sampling rate. The digital signal is then processed by downstream filters in a decimation chain which operate at a second sampling rate that is a fraction of the first sampling rate. In another example, interpolation stages in an interpolation chain in the wireless transceiver circuit operate at a third sampling rate that is a fraction of a fourth sampling rate corresponding to a digital-to-analog converter (DAC). Some ICs support multiple ADC and DAC sampling rates and multiple interface rates within the same IC, such that multiple clock frequencies are needed. The different sampling rates and corresponding clock frequencies can result in coupling spurs due to digital activity coupling to analog activity and introducing artifacts such as sampling clock jitter, which in turn degrade the spurious free dynamic range (SFDR) of the IC. For example, an ADC with a sampling rate of three giga samples per second and digital logic running at 750 MHz (megahertz) might show interleaving spurs every 750 MHz due to the digital activity. To avoid spurs, the comparatively low frequency digital activity is distributed randomly on high frequency clock edges using randomized, or dithered, clock division. The low frequency clock is generated as a rational factor of the high frequency clock. Where the IC supports multiple high frequency ADC/DAC rates and multiple interface rates, more than one rational factor and associated dithered clock division is required.